I. Technical Field
The present invention generally relates to discrete electronic circuit elements, and more particularly, to a trimmable composite multilayer capacitor exhibiting a high quality factor (Q).
II. Related Art
For many years, discrete electronic capacitors have been manufactured using multilayer technology. Generally, layers of conductive metallic electrodes are interleaved with layers of a dielectric material, for instance, ceramic, to form a main capacitor body of a multilayer capacitor. A termination, or a conductive contact, is disposed at each end of the capacitor body. Moreover, each termination is connected to an exclusive set of alternate internal electrodes. In effect, the capacitor body responds like a group of capacitors connected in electrical parallel. The parallel connection is effectuated by the common termination interfacing alternate electrodes. The degree of capacitance achieved is a function of the number of interleaved layers, the geometric area and thickness of each layer, and the dielectric constant K of the dielectric layers.
The historical fabrication of multilayer ceramic (MLC) capacitors and some of the most recently developed methods for manufacturing the same are described in, for example, U.S. Pat. No. 5,046,236 to Wada et al. and U.S. Pat. No. 4,835,656 to Kitahara, both of which are incorporated herein by reference as if set forth in full hereinafter. In general, the fabrication of the capacitor body is a lamination process. Ceramic sheets measuring typically around 1.5 mil in thickness are obtained in green form. A thick film of a metallic electrode paste is screen printed on each ceramic sheet. Next, the ceramic sheets are stacked, pressed, cut, and then sintered in a kiln. Finally, the terminations are disposed at each end of the capacitor body by a conventional dipping process wherein the capacitor body is dipped into a liquified metallic solution, such as silver, and then sintered in a kiln. Afterwards, the terminations may be plated by one or more metallic layers, such as a nickel and/or tin plating layer, if desired, to enhance durability, shelf life, and/or surface mounting processes.
The capacitance values of multilayer capacitors typically fall within a 5%-25% tolerance range as fabricated, even with well controlled fabrication processes. However, more precise capacitance values are required in many circuit applications, and in others, it may be necessary to individually adjust capacitance values of components to custom tune a circuit, the components often referred to as "set-and-forget" devices. This is often accomplished via a functional trimming operation in which portions of the metallic layers in the multilayer capacitors are physically removed. Many varieties of trimming systems have been developed for this purpose and are commercially available in the art. Abrasive trimming systems and laser trimming systems are examples. Laser trimming systems have a number of significant advantages compared to the others, including better accuracy, much greater speed, and cleaner operation.
Recently, there has been an increasing demand for trimmable multilayer capacitors which exhibit a high quality factor Q. A high quality factor Q enables low loss performance of the capacitors at high frequencies, for example, up in the gigahertz (n*10.sup.9 Hz; GHz) range. Traditionally, in the art, ceramic capacitors with a high quality factor Q are fabricated by selecting Class I dielectric materials (0&lt;K&lt;100) having a low dielectric constant K, for example, K&lt;20. For instance, a high density alumina (Al.sub.2 O.sub.3), berylia (BeO), silicon dioxide (SiO.sub.2), calcium titanate (CaTi), or magnesium titanate (MgTi), may be used as the dielectric material for this purpose. U.S. Pat. No. 4,470,096 to Guertin, the disclosure of which is incorporated herein by reference, describes a multilayer capacitor which uses a dielectric material comprised of a composite of both silicon dioxide and alumina.
However, the use of dielectric materials having a low dielectric constant K can be problematic in the multilayer capacitor setting. In order to obtain appreciable capacitance, the dielectric layers must be very thin. This predicament makes the multilayer capacitors very difficult to manufacture and can result in unreliable operation. Specifically, if an outermost electrode is disposed externally on the outer surface of such a multilayer capacitor for the purpose of being trimmed, the trimming may undesirably penetrate completely through the outermost electrode and underlying dielectric layer to thereby substantially damage or expose the next underlying electrode. Exposure can result in a short circuit.
Additionally, with the use of a dielectric material having a low dielectric constant K, the volumetric efficiency, which is generally defined in the industry as the capacitance per unit of volume, is substantially compromised. In other words, volumetric efficiency increases with an increase in the dielectric constant K.
A further problem relative to fabricating trimmable multilayer capacitors exhibiting a high quality factor Q involves the efficiency and accuracy at which a trimmable outermost electrode layer can be depleted. More specifically, if all of the electrodes, including the trimmable outermost electrode, are stacked in the green state and are then sintered together, or co-fired, so as to form the capacitor body, the electrode layers and especially the outermost electrode layer will diffuse or migrate to some extent into the dielectric layers. Consequently, when the outermost electrode is trimmed in circuit, much of the electrode material which has migrated into the underlying dielectric material is not or cannot be depleted by the functional trimming operation.
Further, higher trimming power settings to deplete these diffused regions are not desirable because an extreme risk exists of penetrating too deeply, thereby substantially destroying the underlying dielectric layer and/or electrode. Depletion of the underlying dielectric layer decreases the quality factor Q.
Also, after trimming, a discontinuous, nonplanar, diffused region or perhaps even a distribution of varying-sized diffused islands of electrode material may remain behind in the underlying dielectric layer, resulting in stray capacitances of varying values, thus affecting the linearity of the trimming.
Still another problem in manufacturing a trimmable multilayer capacitor is surface mounting. When solder is applied to the terminations, solder can wick up onto the trimmable outermost electrode. This is especially true in the case where an automated surface mounting process is utilized. The solder on the outermost electrode inhibits trimming. With solder on the electrode, it is almost impossible to trim efficiently and accurately.
In order to prevent solder from migrating onto the trimmable outermost electrode, one known design has disposed the outermost electrode in the form of a "floater" electrode. For example, with the traditional multilayer configuration as described above, the floater electrode is fabricated on the exterior of the capacitor body so that it does not touch either termination, and beneath it, there resides two internal electrodes in the same layer spaced slightly apart and connected to opposite terminations. The foregoing configuration results in two capacitances in series connection between the opposing terminations. However, the foregoing configuration is undesirable because the volumetric efficiency is extremely poor in that the series capacitances are only a half of the total capacitance available in an equivalent parallel design.
Thus, a heretofore unaddressed need exists in the industry for a trimmable composite multilayer capacitor which exhibits a high quality factor Q, before and after trimming, and which is capable of efficient and accurate functional trimming over a wide range while in a circuit.